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CKaru's avatar
CKaru
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7 years ago

NIOS II ELF Download error on 10AX115N4F40I3SG

I am working on a NVME project on Reflex RXCA10X115PF40-PROD Dev kit. The FPGA device on the board is Intel® Arria® 10 GX FPGA 10AX115N4F40I3SG. I use Quartus prime version 16.0.2 Build 222 07/20/2016 SJ Standard Edition for the dproject evelopment. The project includes a NIOSII/e processor. After programming the .sof to FPGA , I genearted the BSP using the sopcinfo in NIOSII SBT & compiled the project. However, when trying to run or debug the program in run as/debug as options in NIOSII SBT, I am getting an error saying the "NIOS II ELF Download Failed".

The same pNIOS II ELF DOWNLOAD ISSUE ON ARRIA10 PROD FPGAroject & Nios II program, when recompiled for 10AX115N4F40I3SGE2 devices [dev kit with Engineering sample FPGA], It runs without any issue.

Can anybody help me to resolve this issue on the dev kit with10AX115N4F40I3SG FPGA.? Thanks in advance.

4 Replies

  • SAR's avatar
    SAR
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    Hi,

    You have to use correct .sopcinfo file (correct device) is used to generate the BSP.

    If .sopcinfo file is generated for 10AX115N4F40I3SGE2 device, same .sopcinfo can not be used for device 10AX115N4F40I3SG to generate BSP.

    Change the device part number in Quartus project and compile and use that .sopcinfo file to generate BSP.

    Regards

    Devil

  • CKaru's avatar
    CKaru
    Icon for New Contributor rankNew Contributor
    7 years ago

    Dear Devil, Thanks for the advice. I had already re-complied the project targeting the 10AX115N4F40I3SG & used the .sopcinfo to generate the bsp, before getting the error.

    Any further thoughts are appreciated.

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    Have you changed the pin assignments?

    Check the Rest pin state, If Reset dip switch is in reset state you may face this issues.

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)

  • CKaru's avatar
    CKaru
    Icon for New Contributor rankNew Contributor
    7 years ago

    Thanks Anand. I am maintaining the same pin assignment in both working board with ES2 device & the problematic board with prod fpga. Except the fpga device installed all the others , including dip switch settings, are same in both boards.

    The external reset pin of the design is pin mapped to a push button which is pulled-up to 1.8V rail. So the reset is activated only when the push button is pressed.

    The reset is connected to a pll ipcore & it's reset output is connected to all other ipcores , including the NIOS II, in the design.