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CKaru
New Contributor
7 years agoThanks Anand. I am maintaining the same pin assignment in both working board with ES2 device & the problematic board with prod fpga. Except the fpga device installed all the others , including dip switch settings, are same in both boards.
The external reset pin of the design is pin mapped to a push button which is pulled-up to 1.8V rail. So the reset is activated only when the push button is pressed.
The reset is connected to a pll ipcore & it's reset output is connected to all other ipcores , including the NIOS II, in the design.