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Altera_Forum's avatar
Altera_Forum
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21 years ago

NIOS II DMIPS

I tested MIPS in Nios II full feature with Dhrystone 2.1. as a result, cyclone ep1c20f400c7 Dev board's MIPS is about 35 DMIPS at 50MHz system clock. bus, stratix ep1s10f780c7 Dev board&#39...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Thanks guys.

I read through CH 16, but I still don't know how many cycles a NiosII multiply takes on my Cyclone chip.

Anybody know conclusively if the next NiosII with the multiplier in LE's will perform exactly as well on a Cyclone as a Stratix I? Will this also give all shifts a one clock execution speed as on Stratix DSP?

This is very important as I am in the process of having my board respun with a Stratix I replacing the Cyclone. It's a BOM budget busting move that I would prefer to avoid if the next NiosII is going to level the performance diffs.

If they are not the same, how will the CycloneII fare vs. StratixI vs. StratixII for upcoming Nios2 cores?

TIA,

Ken