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Honored Contributor
Honored ContributorNIOS II DMIPS
I tested MIPS in Nios II full feature with Dhrystone 2.1. as a result, cyclone ep1c20f400c7 Dev board's MIPS is about 35 DMIPS at 50MHz system clock. bus, stratix ep1s10f780c7 Dev board'...
Altera_ForumHonored Contributor
Honored ContributorKen,
The chapter "Nios II Core Implementation Details" in the Nios II Processor Reference Handbook contains detailed information on cycles-per-instruction and how each core gets implemented in different FPGA families. Have a look. http://www/literature/hb/nios2/n2cpu_nii51016.pdf (http://www/literature/hb/nios2/n2cpu_nii51016.pdf) Also note: As mentioned in another thread, the next release of the Nios II processor will include an option to build the multiply circuitry out of LEs in Cyclone FPGAs, which don't contain DSP blocks. This will allow Nios II on Cyclone to achieve the same multiply in very few clocks, just like on Stratix and Stratix II, at the expense of a few LEs. Matthew
