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Altera_Forum
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10 years ago

Nios II DDR SDRAM read latency

Hi, I’m trying to optimize RAM access from Nios II. when reading 10’000 successive words from ram using iord in a for-loop, it takes 25 clock cycles per read (without loop overhead). To...
Altera_Forum's avatar
Altera_Forum
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10 years ago

The general answer is the align your data :-)

The code will be cached, I presume you have a data cache for most data accesses.

memcpy() will be optimised for long aligned copies.

If you do need to read misalgned items from uncached memory you want to do two 32bit aligned reads and then some shifts and masks.