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Honored Contributor
Honored ContributorNios II DDR SDRAM read latency
Hi, I’m trying to optimize RAM access from Nios II. when reading 10’000 successive words from ram using iord in a for-loop, it takes 25 clock cycles per read (without loop overhead). To...
Altera_ForumHonored Contributor
Honored ContributorHi dsl,
Sorry for the delay and thanks for the good idea :) - For IORD it takes 29cc + 25cc for every additional IORD I add in the loop - For IOWR it takes 6cc + 2cc for every additional IOWR I add in the loop (constant increment for 3,4 or 5 additional IOWRs) - With an empty loop it takes 1cc or 10'000 iterations => meaning the hole loop gets optimized away and the overhead for the (custom made) timestamp is 1cc. So I guess I have to subtract 4cc for loop overhead in my original post :cool:
