Nios II DDR SDRAM read latency

Hi dsl,

Sorry for the delay and thanks for the good idea :)

- For IORD it takes 29cc + 25cc for every additional IORD I add in the loop

- For IOWR it takes 6cc + 2cc for every additional IOWR I add in the loop (constant increment for 3,4 or 5 additional IOWRs)

- With an empty loop it takes 1cc or 10'000 iterations => meaning the hole loop gets optimized away and the overhead for the (custom made) timestamp is 1cc.

So I guess I have to subtract 4cc for loop overhead in my original post :cool: