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Altera_Forum
Honored Contributor
10 years agoNios II DDR SDRAM read latency
Hi, I’m trying to optimize RAM access from Nios II. when reading 10’000 successive words from ram using iord in a for-loop, it takes 25 clock cycles per read (without loop overhead). To...
Altera_Forum
Honored Contributor
10 years agoHow many clocks does your loop take without the IORD() ?
How many does it take if you do the IORD() twice in each loop (with nothing in between)? Or try using signaltap to trace the actual cycle. I've a note that says most reads from SDRAM took 16 clocks, but some took 12. Writes were more interesting: single writes took 2 clocks, but the third took much longer. I assume a two stage 'pipeline' of some sort. DDR will only be worse than SDRAM.