Nios II DDR SDRAM read latency

I found an altera user guide (http://ridl.cfd.rit.edu/products/manuals/altera/user%20guides%20and%20appnotes/external%20memory/emi_ddr_ug.pdf) for the setup I use. There is a chapter "Latency" that states that the HPC II with Cyclone III has a total read latency of 19 clock cycles.

So I know I'm not too far off B)

As you already pointed out, moving data to cache before handling is of course much more efficient. But I will have to see what I can do in this direction...

Thanks

Simon