Nios II DDR SDRAM read latency

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Is the memory controller really so terribly slow

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In short - yes - when you're doing single, random accesses.

However, that is not how DDR memory is intended to be used. To get greater, far greater, access bandwidth, you must access multiple consecutive values with a single command. As Thiago suggests, accessing blocks of memory will improve your access bandwidth vastly. So, to use DDR efficiently you need to cache chunks of memory from it and then use the cache. Latency to your cache'd data will be a couple of clock cycles at worst.

If you genuinely need single, random access to external memory, then you need to consider SRAM or SSRAM. With 29 clock cycles per access with DDR, I suspect you'll find either of these will be just as quick.

Regards,

Alex