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Honored Contributor
Honored ContributorNios II DDR SDRAM read latency
Hi, I’m trying to optimize RAM access from Nios II. when reading 10’000 successive words from ram using iord in a for-loop, it takes 25 clock cycles per read (without loop overhead). To...
Altera_ForumHonored Contributor
Honored ContributorHi Thiago,
Of course reading a large block of data to a local array and then go over it is more efficient - assuming you are willing to provide enough onchip memory. But this is not the point, it's more a general question: Is the memory controller really so terribly slow, or am I missing something. Best Regards Simon
