--- Quote End ---
Hardware, definitely.
If you want a free-running, steady clock signal, you just need a peripheral to generate it. Try this Verilog:
...
--- Quote End ---
Hi Mike,
thanks a lot for your advice. I was trying to follow the steps you showed me in previous post. Everything went fine until I started the compilation of my project in Quartus II.
Here, in Pre-compilation (or Analysis) phase I get the following error:
"" Error: Node instance "the_ClockGenerator" instantiates undefined entity "ClockGenerator" ""
Clicking this message takes me into the Verilog design file of the ClockGenerator module.
I tried to browse the forum to find any hint, but couldn't find anything useful.
Do you have any idea how to resolve this problem?
Honored Contributor
