NIOS-II Cyclone II devboard timer problem

--- Quote Start ---

originally posted by cableguy@Oct 27 2005, 03:54 AM

what would you suggest to me to create such a signal, either by software or hardware, so higher frequency can be reached?

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=10623)

--- quote end ---

--- Quote End ---

Hardware, definitely.

If you want a free-running, steady clock signal, you just need a peripheral to generate it. Try this Verilog:

module ClockGenerator
(
    input clock,
    input reset,
    input chipselect,
    input write,
    input  writedata,
    output reg clockout
);
reg  count, limit;
always @(posedge clock, posedge reset)
    if(reset) begin
        count <= 0;
        limit<= 0;
        clockout <= 0;
    end
    else begin
        if(limit == 0)
            clockout <= 0;
        else if(count == limit) begin
            count <= 0;
            clockout <= ~clockout;
        end
        else
            count <= count + 1;
        if(chipselect && write)
            limit<= writedata;
    end
endmodule

Take that, use SOPC Builder to make it into a component (set the pin types to the same as their names, except "clockout" should be "export" type), and add it to your system. Let&#39;s say you name it "clock_gen". When you generate the system, you&#39;ll have a clockout_from_the_clock_gen (or clockout_to_the_clock_gen? I can never remember) pin that you hook up to your ADC&#39;s clock.

In software, you just have to# include "system.h" and <io.h>, then you can use "IOWR(CLOCK_GEN_BASE, 0, x)" to change the divisor to x (where output clock frequency = sysclock / (2 * (x + 1)) ), and "IOWR(CLOCK_GEN_BASE, 0, 0)" to turn it off.