NIOS II Custom Instruction access to CPU Regs'

Hi Stefaan,

thanks for your information. That seems to be strange I thought if I am using the F core it would take only 1 cycle to store and load data from internal ram. In the SOPC designer the internal ram is created with no wait states, so i thougth I only have to look at "fundamental slave read transfers" of avalon bus -> so it is 1 cycle. The same is for the write transfer (Avalon Bus Specification Reference Manual pages 27 and 37). Did I missunderstood something ?

Holger