Nios-II core reset

There are no provisions to do that easily. However you could always use an interrupt coming from external logic that will trigger the reset.

In your system it sounds like all you need to do is bring a signal out from this other master and have the NIOS II wait on this signal (i.e. a done signal). Not only will that work but also when the other Master is done, the NIOS II core is already up and running and you don't have to wait for all the initialization. The only way this will not work is if the contents that are programmed into SDRAM is where your code boots from (then what you want to do is the only option).

The only problem with having seperate reset signals in your system is that there are a lot of things that can go wrong if everything is not reset properly, and this is probably the main reason why that kind of functionality is not in SOPC builder. However, I do like the idea of having a seperate reset for the NIOS II core that is tied to a global reset for the entire system. Things can go wrong with that configuration as well but it is more managable then a big list of reset signals.