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Altera_Forum's avatar
Altera_Forum
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14 years ago

nios ii console shows nothing

Hi,

I am new to nios ii and find some strange things when running just hello_world or memory_test examples programs...

First it works fine with these simple programs, but when I do synthesis again and run again, nothing appears in the Nios II console.

The downloading and verifying are good as below:

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Processor is already paused

Initializing CPU cache (if present)

OK

Downloading 00080020 ( 0%)

Downloading 01000000 ( 0%)

Downloading 01010000 (60%)

Downloaded 107KB in 1.8s (59.4KB/s)

Verifying 00080020 ( 0%)

Verifying 01000000 ( 0%)

Verifying 01010000 (60%)

Verified OK

Starting processor at address 0x01000000

However after showing this the Nios II console is just blank.

I also tried program the .soc file again or do synthesis again or build the SOPC system again, but it still doesn't work...

I am sure the pin assignments are ok and it works before.

Any one can tell me the reason?

Many thanks.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi Cris,

    I added some timing constraints to my project.

    Although there is a Critical Warning doesn't meet the timing requirement,

    the project works most of times.

    Thank you for your help!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    "most of the times" is not good. It must ALWAYS work.

    If you recognized there are critical timing paths you have to fix them. It can affect your system behaviour in very subtle and impredictable ways. Problems could appear also in other modules, not only jtag uart.

    First of all make sure you activated the timing driven synthesis option in Quartus settings.

    Sometimes these timing warnings can be avoided by placing jtag_uart behind a cc bridge and operating it at a lower frequency with respect to system clock. This can help a lot with meeting timing requirements; the price paid is a slight increase system complexity, then more fpga resource used.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi Cris, I tried to solve those critical timing warnings, but with the SDC file, the warnings appear just with 'create clock' lines. It is just:

    # Original Clock Setting Name: CLOCK_50

    create_clock -period "20.000 ns" \

    -name {CLOCK_50} {CLOCK_50}

    ---------------------------------------------

    create_clock -period "50.0MHz" [get_ports GPIO_1[16]]

    create_clock -period "50.0MHz" [get_ports GPIO_1[0]]

    I really don't understand why, CLOCK_50 is a real 50MHz clock pin and

    when I comment the last two lines the critical warning is still there.

    Could you help me?