nios ii console shows nothing

"most of the times" is not good. It must ALWAYS work.

If you recognized there are critical timing paths you have to fix them. It can affect your system behaviour in very subtle and impredictable ways. Problems could appear also in other modules, not only jtag uart.

First of all make sure you activated the timing driven synthesis option in Quartus settings.

Sometimes these timing warnings can be avoided by placing jtag_uart behind a cc bridge and operating it at a lower frequency with respect to system clock. This can help a lot with meeting timing requirements; the price paid is a slight increase system complexity, then more fpga resource used.