Nios II 5.0 - CPU Revealed

Now that Nios II 5.0 is officially released, here are details of the improvements to the CPU.

BTW, Nios II just jumped from version 1.1 to version 5.0. The change was made to sync up

with the Quartus II version numbers. This makes it clearer that Nios II should be used with the

matching Quartus II version.

Here's a summary of improvements:

- New data cache

- Tightly coupled memories

- New FLUSHDA instruction

new data cache

The new data cache is available for the Nios II/f. It offers the following advantages over the previous data cache:

- Support for 16-byte or 32-byte lines. This provides higher performance for many designs especially those

that use DRAM.

- Can use M-RAMs

- Faster non-cacheable accesses to memory.

- A one-line victim buffer that reduces stalling when a line miss to a dirty line occurs.

The new data cache is selected by specifying a line size of 16 or 32 bytes in the Nios II wizard.

The old data cache is still available by selecting a line size of 4 bytes.

Any example designs in the Nios II kit that contain DRAM use the new data cache.

The data cache in the Nios II/f is now optional. Previosly, if you didn't want a data cache, you had

to use the Nios II/s with a 5-stage pipeline. Now you can use the Nios II/f with its advanced 6-stage pipeline

which offers better performance. It takes fewer cycles to execute some classes of instructions and can run

at a higher frequency.

In this forum, there were complaints about the number of cycles of overhead for the Nios II/f to directly access

Avalon slaves (bypassing the data cache). With the old data cache (4-byte line), the overhead is 3 cycles for

non-cacheable loads and 2 cycles for non-cacheable stores.

With the new data cache (16/32-byte line), the overhead is reduced to 2 cycles for non-cacheable loads and 1 cycle

for non-cacheable stores. This matches the overhead of the Nios II/s core or the Nios II/f core without a data cache.

The new data cache is a writeback cache that is direct-mapped (just like the old data cache).

tightly coupled memories

Tightly coupled memories are an exciting new feature which allow high-bandwidth, low-latency access to on-chip memories.

The Nios II accesses tightly coupled memories without any cycle overhead.

It can perform one load/store to a tightly coupled data memory and one instruction fetch to a tightly coupled instruction memory

every cycle. There are never pipeline stalls when accessing a tightly coupled memory.

Previously, on-chip memories had to be connected to the Nios II using the normal Avalon instruction master

and data masters. Access to memories connected to these masters incurs a penalty of one or more cycles

due to the overhead of Avalon.

Now with support for tightly coupled memories, the Nios II uses new tightly coupled masters which

connect directly to the on-chip memories and have no overhead.

The Nios II/f supports both tightly coupled instruction and tightly coupled data memories.

The Nios II/s support only tightly coupled instruction memories.

There is support for up to 4 tightly coupled instruction memories and 4 tightly coupled data memories.

The Nios II creates a new master port for each tightly coupled memory.

The number and types of tightly coupled masters are specified by the user in the Nios II wizard in SOPC Builder.

Tightly coupled memories must be 32 bits wide and have a read latency of one cycle,

a write latency of zero cycles, and no wait states. Currently only on-chip memory components are

supported as tightly coupled memories. DRAM is not supported as a tightly coupled memory

because it has variable latency.

If there is at least one tightly coupled instruction memory, the instruction cache can be removed.

This is potentially a good choice for systems with small code sizes that fit in an on-chip memory.

Since all on-chip memories are dual-port capable, one port can be used to connect to a tightly coupled

master on a Nios II and the other port can be connected to other Avalon masters such

as another Nios II or a DMA controller. This provides a powerful method to stream data in and out of

the Nios II. The other master transfers data in/out of the tightly coupled memory and then Nios II

can access this data without any stalling.

Code for interrupt handlers and the associated stack can be placed in tightly coupled memories

to reduce interrupt latency.

new flushda instruction

The existing FLUSHD and new FLUSHDA instructions both flush data cache lines.

However, the new FLUSHDA instruction does a full address comparison and only flushes

the line if the complete address matches. The FLUSHD instruction ignores the tag portion

of the address so always flushes a line.

Note that this is only the behavior for the new data cache.

The old data cache treats FLUSHDA instructions like FLUSHD instructions.

The FLUSHDA instruction improves the performance of multi-master or multi-CPU systems when a buffer needs

to be flushed from the cache to maintain coherency.