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Hi all,
- I am already having a design that communicates with x86 processor from NIOS II using the shared memory over the PCIe interface.
- With new design my aim would be to reverse the shared memory and place it on the x86 processor DDR memory instead of FPGA SSRAM.
- And aware of this would require some complex address translation logic to be included in the fabric.
- I came to know that, "txs" signal in the PCIe interface ip core will access the host memory, but I want to know how that signal will access DDR memory or some other internal memory on x86 processor.
- Also I like to know how DDR memory in x86 processor is used?
- I am interested to know if someone has already achieved something similar and if it is possible to get hold of a reference design for this or related configuration to start with.
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Hi Varun,
This link will take you to various Altera Reference designs for PCIe. //
www.altera.com/products/reference-designs/ip/interface/m-pci-express-refdesigns.html The TXS port is an Avalon MM slave port used to generate Inbound PCIe Read and Write operations to a RC.
I am not familiar with "DDR memory in the X86 processor" ... but Host system will have a memory map for Memory / Register space that is accessible from the PCIe RC. I assume you want to get a DMA operation from the EP to the Host DDR memory.
Regarding translations, the PCIe IP / Avalon Bridge has local translation tables configurable by the user to be a static translation or configured by NIOS II core. These translations can be 32 bit Avalon MM-> 32 bit PCIe address or 32 bit Avalon MM -> 64 bit PCIe.
There are other reference designs like Gen3x8 with DMA that use a 64 bit Avalon MM address -> 64 bit PCIe address without any translation.
Best Regards, Bob
Honored Contributor
