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Altera_Forum
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12 years ago

NIOS II 32 bit data master -> Avalon MM PCIe 64 bit TX slave

I had a system working where the DMA controller ( 64 bit ) was reading and writing to the TX port of the PCIe TX port . I now have a situation where I want the NIOS II data master ( 32 bit ) to r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi all,

- I am already having a design that communicates with x86 processor from NIOS II using the shared memory over the PCIe interface.

- With new design my aim would be to reverse the shared memory and place it on the x86 processor DDR memory instead of FPGA SSRAM.

- And aware of this would require some complex address translation logic to be included in the fabric.

- I came to know that, "txs" signal in the PCIe interface ip core will access the host memory, but I want to know how that signal will access DDR memory or some other internal memory on x86 processor.

- Also I like to know how DDR memory in x86 processor is used?

- I am interested to know if someone has already achieved something similar and if it is possible to get hold of a reference design for this or related configuration to start with.