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Altera_Forum
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12 years ago

NIOS II 32 bit data master -> Avalon MM PCIe 64 bit TX slave

I had a system working where the DMA controller ( 64 bit ) was reading and writing to the TX port of the PCIe TX port . I now have a situation where I want the NIOS II data master ( 32 bit ) to r...
Altera_Forum's avatar
Altera_Forum
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12 years ago

After some discussion I don't believe read latency is an issue as long as the reads commands arrive at the RC at random times. This will mean the read of the

flag will at some time occur just after the system core has set the flag ... I still need to get the posted writes in the bridge at the same time as the read completion

to check for PCI ordering rule violations. The device driver guy said I need to add wmb() between the posted writes to the endpoint and the setting of the flag in

the system memory.