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Altera_Forum
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12 years ago

NIOS II 32 bit data master -> Avalon MM PCIe 64 bit TX slave

I had a system working where the DMA controller ( 64 bit ) was reading and writing to the TX port of the PCIe TX port . I now have a situation where I want the NIOS II data master ( 32 bit ) to r...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Possibly stall/rerun the PCI transfer for long enough to setup the race condition?

PCIe will never be low latency. A PCIe request is an hdlc frame containing the address, length (etc) and any data, this has to be decoded and verified (etc) before being actioned and then the response hdlc frame generated. All this takes time.

To efficiently use PCIe the whole logical interface has to be arranged to use DMA wherever possible and to minimise the number of PIO reads.