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900ns wouldn't surprise me.
Single transfers into the fpga are similarly slow (IIRC 600-700ns when running the FPGA at 100MHz).
PCIe is a high-throughput high-latency 'bus' and isn't really suitable for PIO accesses.
I've not timed transfers into other PCIe slaves to see how slow they are, but they won't be fast.
The elapsed times are slow because PCIe is a comms protocol, not a bus protocol.
So even for relatively low throughput you need a dma controller to request single PCIe transfers for upto 128 bytes (typically the limit for a single transfer).
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DSL, sounds like I'm in trouble ...
I tried the 32 bit word read from the other direction ... RC reading the FPG memory .. and got a similar result around 900 nS from when the read command is received and the start of the read completion.
In addition our Linux DD guy suggested to time the RC Config read ... I timed the config read of the Command register and it also was say 840 nS.
In this case there is no interaction on FPGA fabric or memory ... just a register read. I still can't explain this since the FPGA and ARM SOC are running
different IP maybe the same ref_clk and the results ae about the same ... why am I in trouble ... I am trying to test for a race condition and to test for that , I need the window between read and completion to be small enough to identify a race involving PCI ordering issues.
I will need to see if there is a work around.
Best Regards, Bob
Honored Contributor
