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Altera_Forum
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21 years ago

Nios I - Wrong IRQ Vector

I recently noticed a problem with a Nios (not Nios II) design implemented on an APEX EP20K device. At initialization, I set all entries in the interrupt vector table to point to the same routine: it ...
Altera_Forum's avatar
Altera_Forum
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21 years ago

The two external octal UART interrupt signals are inverted (since they are active low), then connected to two bits of a standard Nios PIO register with "irq_type=LEVEL". Is it still necessary to synchronize them with the Nios clock before bringing them to the PIO?

The other interrupt is from a standard Nios timer (so I would assume it is inherently synchronized). The interrupt signals from the Nios PIO and timer are presumably wired up to the processor according to the SOPC builder defaults.

I'm just writing the software, but I'll pass this suggestion on to the engineer who does the hardware design.

Thanks!