Honored Contributor
Honored Contributor
i've been testing the nios ii fpu performance and it seems to be very bad unless i'm missunderstoding something. when running the tutorial example i get the following results:
addition: time(clocks) no fpu approximately 254 cycles
with fpu approximately 22 cycles
similar results for sub and multiply instructions.
in my opinion 22 cycles is too much for an fpu. i've been searching the web and there are other processor with the fpu integrated within the pipeline which perform operations in only 1 cycle (plus latency).
is the nios ii fpu integrated within the pipeline?
how many cycles does it itakes to perform an operation?
the information provide by altera doesn't talk too much about this issues.
thanks in advance,
luis
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--- Quote End --- You may have a look at www.opencores.org. There is a good FPU project. This implementation is pipelined. According to the doc: - Nr. of logic elements : *3468 - fmax: 100 MHz -Clock Cycles: Addition/Subtraction 7 Multiplication 12 Division 35 Square-root 35 Hope this helps. BR
