Nios Development kit

Can you post the link to your other thread in here. Reading this one it sounds like something went wrong and now you are trying to determine if the board is toast. Here's a pretty good safe design, bring in the 50MHz clock input and reset, wire them to a wide counter, then take 8 bits out of the counter and wire those to the LEDs (to figure out which bits to wire, take the clock period (20ns) and crunch the numbers to find out what bits to use so that it's not too slow, or so fast you can't see them switching).

Also if this configuration doesn't seem to stay, have you been setting unused I/O to "tristate" in Quartus II? I accidentally made a design that kept toggling a bit going to the CPLD that would reset the design all the time due to the unused I/O not be driven to tri-state (maybe you have done the same).

Good-luck