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Altera_Forum
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14 years ago

Nios debugger and DDR2 problem

Hi everybody, The problem is downloading the nios software into the ddr2 memory. I use Quartus 11.sp1 with Qsys to build a system with internal RAM and a DDR2 Uniphy controller. The nios cpu...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi,

no response here and no Avalon-MM compliant cache found on the web so I will try and implement it myself :( .

I want to do this as a Qsys component so I can insert it in Qsys between NIOS and the DDR2 interface. I have started now with the component editor and first added Avalon-MM slave and master interfaces. Now I have the problem that I cannot find the "beginbursttransfer" signal on the master interface in the component editor. I found and added "burstcount" on the master interface. I found and added both those ports on the slave interface so I think I know where I should find this. I guess there is some prerequisite for the beginbursttransfer signal that I am not aware of ... looking through the Avalon spec I did not find this.

Maybe somebody knows this.

Best regards

flintstone