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Altera_Forum's avatar
Altera_Forum
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14 years ago

Nios debugger and DDR2 problem

Hi everybody,

The problem is downloading the nios software into the ddr2 memory.

I use Quartus 11.sp1 with Qsys to build a system with internal RAM and a DDR2 Uniphy controller. The nios cpu has cache memory for data and instruction.

The DDR2 Memory on my custom board has a 16bits width data bus and it's data mask bits (DM 0 and 1) and tied to ground and not connected to the FPGA.

Running a ddr2 memory test program from the internal memory is successful, as long as the memory is accessed in burst mode. But if the cache is bypassed (write commands IOWR_32DIRECT, ..), then the data in DDR2 is corrupted. The Controller makes always 4 burst accesses and so the word before or after the addressed memory word is corrupted.

It is the same behavior when I try to download the software directly to DDR2 via debugger. Here is every other word corrupted too.

The question is:

Are the DM bits tied to ground the cause of this problem?

And if yes, is there any working configuration for Nios, DDR2 Uniphy ... ?

Thank you for any hints

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi,

    I work together with the thread opener on this issue and will give an update here: I have looked at the issue in simulation and think, that the problem really arises due to the DM~ pins being tied to GND: For IOWR_32DIRECT Macro accesses it can be seen that the DM~ pins internal to the design are switching as if they should mask out the unused words in the burst access ... if these pins were connected to the memory the thing should work imho.

    Question is how to easily fix this: One idea would be to place another small transparent cache between the NIOS core and the DDR2 interface component. I would already have done that but I cannot find a cache component in the Qsys component library ... maybe someone got a hint where to find one.

    Best regards

    flint
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi,

    no response here and no Avalon-MM compliant cache found on the web so I will try and implement it myself :( .

    I want to do this as a Qsys component so I can insert it in Qsys between NIOS and the DDR2 interface. I have started now with the component editor and first added Avalon-MM slave and master interfaces. Now I have the problem that I cannot find the "beginbursttransfer" signal on the master interface in the component editor. I found and added "burstcount" on the master interface. I found and added both those ports on the slave interface so I think I know where I should find this. I guess there is some prerequisite for the beginbursttransfer signal that I am not aware of ... looking through the Avalon spec I did not find this.

    Maybe somebody knows this.

    Best regards

    flintstone
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    flintstone, did you ever find beginbursttransfer? How did you solve your problem?