nios custom ip interrupt questions.

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf

See Chapter 4 Avalon Interrupt Interfaces.

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4.1 Interrupt Sender

An interrupt sender drives a single interrupt signal to an interrupt receiver. The timing of the

irq signal must be synchronous to the rising edge of its associated clock. irq has no relationship

to any transfer on any other interface. irq must be asserted until acknowledged

on the associated Avalon-MM slave interface.

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