Forum Discussion
Altera_Forum
Honored Contributor
13 years agoNo need to quote all the post ....
If the object code is the same, then maybe the difference is caused by additional instruction cache loads because code is now sharing instruction cache lines (the overall address map will probably have changed). The data addresses are unlikely to be significantly different - but might be. Running code from tightly coupled instruction/data memory (and with the dynamic branch prediction disabled) I got consistent timings that match the expected values.