Nios C-Code Size

Thankyou Guys I knew that there had to be an easy way.

I certainly agree with your comments about making an absolutely minimum system. I have been working with Xilinx for many years and so I am relatively new to Altera.

In our Xilinx designs I was using a small microcontroller for all of this type of housekeeping stuff ... originally it was the KCPSM and then renamed PicoBlaze.

Now don't shoot me I fully appreciate that the Pico is a completely different beast to Nios - only 8bit core and I had to write code in assembly language rather than C.

The end result though is that even though it might take me a couple of weeks to get it to work I ended up with designs that would be nothing more than a handful of gates and 1 or 2K bytes of code.

I thought about using a much simpler 8-bit MCU design for Altera [and there is even a code-compatible version of PicoBlaze which can be compiled for any FPGA] but I love the way that Nios2 is integrated into the workflow its very nice and convenient to use. These days I am less concerned about how many gates I am using up but the trouble is that even a very basic program needs >20K of RAM before it does anything useful and Block RAM is always in short supply.

I am afraid I don't know enough about the IDE or C-code development in general to start pulling out and discarding Libraries and other such things but a reference design or even a set of instructions would be a very valuable thing !

BTW The optimization setting was a very useful tip - took me a few minutes to find out where to change it but it saved nearly 5K of code space on this design and remarkably everything is still working !