Nios behaving erratically?

Yes, I am working on a project that has the problem you describe. I have some "magic" printf's which make some code "work". Luckily, this code is part of a feasibility test and is not required for the product and have abandoned that part of the project. However, this problem is extremely annoying and frustrating. My project is running completely out of on-chip RAM.

I have had similar problems with when making minor changes in the VHDL code and re-fitting or when updating my QII software. The second problem suggests a timing problem within the part. My project uses on-chip RAM for shallow LPM FIFOs to pass data across clock boundaries.

Perhaps we can find some commonality in our problems we can get Altera to look at the problem.

My project:

Cyclone I : EP1C20F400C7

Total LE: 11,468/20,060 (57%)

Total pins: 228/301 (76%)

Total Memory Bits: 209,920/294,912 (71%)

40MHz system clock

I suggest if anyone finds a cause and/or solution to please post it to the forum.

Thanks.

Steve