Forum Discussion
Altera_Forum
Honored Contributor
14 years agoThanks Cris ....very clear!!!
another question..!! In my component...I have clearly to manage the the avalon MM bus signals and so modifying my entity and architecture using an appropriate interface logic block!...Is it correct??? I ask this question..because my initial logic block has 4 signals as control input (Start, Reset, Clock, Configure), 2 signals as control output (conf_done, packet_ready) and a data_packet (32bit) as data output. Hence I should modify the block to adapt it to MM-avalon interface...correct??? So, If ,from Nios, I wanted to make my component start or configure or reset...I should create a number of different register to write in my component in order to allow to show it what it has to do...Am I wrong???