Nios 2 IDE download verification error

yes, I wrote nonsense above. The contents of EPCS is not visible in NIOS address space. It is the epcs-controller located at address 0, which is the restart address. But the problem is still the same.

This is part of my firmware.objdump file:

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .entry        00000020  00000000  00000000  000000b4  2**5
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .exceptions   000000cc  00200020  00200020  000001b0  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .text         00022d44  002000ec  002000ec  0000027c  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  3 .rodata       00017be0  00222e30  00222e30  00022fc0  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  4 .rwdata       00002ebc  0023aa10  0023aa10  0003aba0  2**2
                  CONTENTS, ALLOC, LOAD, DATA, SMALL_DATA
  5 .bss          00010280  0023d8cc  0023d8cc  0003da5c  2**2
                  ALLOC, SMALL_DATA
  6 .epcs_controller 00000000  00000020  00000020  0003da5c  2**0

There is a section .entry located at 0x00000000 (the epcs-controller base address). All firmware is placed in SRAM (base = 0x00200000).

SYMBOL TABLE:
00000000 l    d  .entry    00000000 
00200020 l    d  .exceptions    00000000 
002000ec l    d  .text    00000000 
00222e30 l    d  .rodata    00000000 
0023aa10 l    d  .rwdata    00000000 
0023d8cc l    d  .bss    00000000 
00000020 l    d  .epcs_controller    00000000

and here is the code placed in section .entry, linked to address 0:

Disassembly of section .entry:
00000000 <__reset>:
     */# if NIOS2_ICACHE_SIZE > 0x8000
    movhi r2, %hi(NIOS2_ICACHE_SIZE)# else 
    movui r2, NIOS2_ICACHE_SIZE
   0:    00810014  movui    r2,1024# endif
0:
    initi r2
   4:    1001483a  initi    r2
    addi r2, r2, -NIOS2_ICACHE_LINE_SIZE
   8:    10bff804  addi    r2,r2,-32
    bgt r2, zero, 0b
   c:    00bffd16  blt    zero,r2,4 <__alt_mem_epcs_controller+0x4>
1:

This is the code at the restart address, linked automatically to my firmware. So the first dword at address 0 should be: 0x00810014. But when I start debugger without loading software, I can read a memory map at address 0 but find the code of the boot-copier &#39;epcs_controller_boot_rom.hex&#39;. The code of this <__reset> function above in section .entry can be found at the start of the firmware placed in EPCS behind the FPGA configuration.

So the debugger expects this __reset-code at address 0 where the boot-copier resides in ROM. Perhaps this __reset-code is position independent and therefore also linked to address 0 ?

I&#39;m a little bit confused what happens. Anybody else ?

Explanations welcome.

Mike