Nios 2 IDE download verification error

Hi Jesse,

thanks for your detailed explanation. But in my case, EPCS contains at address 0 a FPGA configuration and behind it a firmware, which is compiled and linked also to address 0 (restart vector) but will be relocated to its original address by a boot loader after restart. But this offset is obviously not taken into account by this verification process which compares against address 0 (as shown above) and aborts debugging due to this assumed error.

So what options do I have to debug this firmware ?

Mike