NIOS + VHDL logic simulation ?

Hello,

I am new to embedded soft and hard processor in FPGA. I am comfortable in VHDL. I would like to know if VHDL block linked to NIOS processor can be simulated completely and verified w/o development board ?

for example : A VHDL block reads input pins and modifies the data before passing it to NIOS. NIOS in turn does some modification before passing the data to output pins of FPGA... Is it possible to simulate the whole stuff in Quartus through testbench w/o development board ?

If yes...could someone redirect me to some simple very well explained example on internet showing the same step by step...

Thanks and regards

Nisheeth