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Altera_Forum's avatar
Altera_Forum
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10 years ago

NIOS + Pipeline Bridge

How can someone make memory imported through an MM pipeline bridge visible in Eclipse/NIOS? On BSP editor I can only see the on-chip memory. I'd like to place .rwdata .rodata on that section up...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Oh so it's a different .tcl file. I'm referring to the TCL file you create through "File... export hardware as tcl". Is that the same?

Then the qsys project is loaded up in top/verilog. Does this tcl file get parsed again in this specific case?