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Altera_Forum
Honored Contributor
13 years agoYou don't see the slave transfer because when you use a pointer access the CPU just writes to its data cache. The written value will only be written to your slave during a cache line flush.
Your "appreciable cycle gap" isn't due to the slave latency, it's just that the CPU requires several cycles to execute your instructions. Sure if you use bursts al the values will be written faster, but before that, the CPU will use about the same amount of cycles to fill the data cache than what you measured with the IOWR instructions. So using bursts will not make the total execution time any shorter.