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Altera_Forum's avatar
Altera_Forum
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13 years ago

NIOS : IOWR works fine but writing through a pointer not

I have two problems with a generic NIOS system with data and instruction caches. 1. A Avalon MM slave is attached to NIOS system. A write to the slave is successful through IOWR. However, wit...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Many thanks for the reply.

I received some feedback for question 2 and my comments are below.

It's known that IOWR() bypasses cache. MMU is not used in this example case. Data cache is added to support burst transfer. The nios is connected to avalon master which is also configured to support burst transfer.

I would like to support burst transfer to the slave and that's the reason for adding cache...If its not correct, then how to support burst transfer with the slave while nios acts as master on the avalon mm fabric.

There is appreciable cycle gap between two IOWR/IORD commands and the gap makes these not that much attractive.

Could any please also respond to question 1.