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Yes there is no problem with doing that, but the NIOS program needs to get copied into DDR one way or another. If the NIOS can't boot from a small (parallel) flash, then you will likely need an onchip memory (ROM) with a bootloader program in it. This is the approach used by the EPCS NIOS boot method, where the small bootloader has the NIOS copy the executable from EPCS flash to your external memory.
http://www.altera.com/support/examples/nios2/exm-alt-boot-methods.html --- Quote End ---
reading the documentation about boot loaders I understood that the standard boot loader should be able to load the program from the flash to the DDR RAM, but it is required a small amount of onchip memory to run the bootloader, it is right?
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Something else to consider is that minimizing resources including trimming the NIOS cache is going to result in very low performance when executing from DDR.
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how much cache it is "advisable" to use? In my system Nios will only receive packets from UDP and make data available to FPGA custom logic and vice versa.
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Did you regenerate the BSP after changing the FPGA? It sounds like the base address of those peripherals changed.
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of course yes!
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There is a couple good examples:
http://www.altera.com/support/examples/nios2/exm-net-std-de.html http://www.alterawiki.com/wiki/nios_ii_udp_offload_example --- Quote End ---
thanks! the alterawiki example seems very interesting
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