Binome,
I got a Terasic DE0-nano board with a Cyclone IV FPGA. My design is writing data in the memory. I use a NIOS II softcore too and I'd like it to read the FPGA memory and the data I wrote in a hardware-way. Can I do that?
I have used the SDRAM with a Nios a few time. So yes it is possible.
In fact only the other day I wrote a blog post about it here:
http://geobyjmhembeddedengineer.blogspot.co.uk/2014/05/connecting-sdram-to-nios-ii-on-de0-nano.html There is also a good app note by altera:
ftp://ftp.altera.com/up/pub/altera_material/11.0/tutorials/verilog/de0-nano/using_the_sdram.pdf Hope this helps
geobyjmh