New component never compiles in Quartus II

Hi all,

after some help from Mike DeSimone (thanks!) I created a new component in SOPC builder from this Verilog file:

module ClockGen
(
   input clock,
   input reset,
   input chipselect,
   input write,
   input  writedata,
   output reg clockout
);
reg  count, limit;
always @(posedge clock, posedge reset)
   if(reset) begin
       count <= 0;
       limit<= 0;
       clockout <= 0;
   end
   else begin
       if(limit == 0)
           clockout <= 0;
       else if(count == limit) begin
           count <= 0;
           clockout <= ~clockout;
       end
       else
           count <= count + 1;
       if(chipselect && write)
           limit<= writedata;
   end
endmodule

---which should function as hardware clock generator.

I saved this code into hw_clk.v file and added to User Logic components in SOPC builder as ClockGen component. Then I instantiated it in my system as AD_CLK_HW component and re-generated the system. Until here everything went fine, but when I refresh the .bdf file in Quartus II and start compilation, I get this error:

<div class='quotetop'>QUOTE </div>

--- Quote Start ---

Error: Node instance "the_ClockGen" instantiates undefined entity "ClockGen"[/b]

--- Quote End ---

Here the compilation stops. I received some feedback from Mike again to resolve the problem by instantiating the component in the SOPC builder under different name, but it hasn&#39;t helped at all.

I would really appreciate any help with this problem....