Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

New component in SOPC builder

Hi,

I am trying to make a basic up/down counter as a component in SOPC builder. An 'en' signal will tell the counter whether to count up or down. I was planning to give this en through NIOS II. I added the VHD design file in edit component in SOPC builder. Then I followed two designs, which gave respective errors -

In the first design, I took count and en as conduit signals and exported them out, in component making. After making the component in builder, when I added it in design through our SOPC, then no corresponding base address was being shown in it.

In second design, in order to get base address, I added one more signal en_1 (pseudo signal, not being used in VHDL code, but only declared in entity). I took this as an avalon tristated slave interface and the signal as read signal. Now, when I added the component using SOPC, then base address was being shown. But, now base address and end address being shown are same. (Please have a look on design_counter_2 screenshot).

Please comment on how to assign base address to these newly added components and please point out any mistakes in these designs as in my component after doing "AUTO ASSIGN BASE ADDRESS", the base address and high(end) address of my component were same which should not happen.

Thanks and Regards,

Saransh

12 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Could you please be specific to which type of component should we be adding to NIOS and which type of signals be given control to NIOS?

    I was planning to add this basic component using this small signal, before going to any other bigger ip and controlling it through address and data.

    So, i added this component with NIOS having control over only enable 'en' signal
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    i can't give you and an VHDL example as i use verilog HDL

    but have a look at avalon memory-mapped slave template (http://www.altera.com/support/examples/nios2/exm-avalon-memory-slave.html?gsa_pos=1&wt.oss_r=1&wt.oss=avalon slave template)

    to understand how you can include your own functionality as an sopc component.

    mainly you need some signals like chipselect, write, writedata, read, readdata and clock & reset

    you need to code a register that holds your signals you want to control via nios

    this register is read via the read signal and delivers its content via readdata

    and vice versa, write & writedata to store the information.

    use chipselect to enable the access

    now you can use one of these bits from that register as enable for your functionality