Honored Contributor
Honored ContributorThis is the code for first design
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity count_led_0 is port(clk : in std_logic; rst : in std_logic; count : out std_logic_vector(3 downto 0); en : in std_logic; ); end entity count_led_0; architecture rtl of count_led_0 is signal counter : std_logic_vector(3 downto 0); begin process(clk,rst,en) begin if(rst='1') then counter <= "0000"; elsif (clk'event and clk='1')then if (en='1') then counter <= counter + '1'; else counter <= counter - 1; end if; end if; end process; count <= counter; end architecture rtl; -- of count_led_0 And following is code for second design library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity count_led_0 is port(clk : in std_logic; rst : in std_logic; count : out std_logic_vector(3 downto 0); en : in std_logic; en_1 : in std_logic ); end entity count_led_0; architecture rtl of count_led_0 is signal counter : std_logic_vector(3 downto 0); begin process(clk,rst,en) begin if(rst='1') then counter <= "0000"; elsif (clk'event and clk='1')then if (en='1') then counter <= counter + '1'; else counter <= counter - 1; end if; end if; end process; count <= counter; end architecture rtl; -- of count_led_0
