Need PCIe Driver of X86 PC for DMA Read/Write Support on QSYS Cycleon V FPGA System

Should work.

The DMA engine needs to do correctly sized avalon burst cycles into the pcie avalon slave.

I did pipelined avalon reads from the internal memory block.

Didn't bother overlaping the reads and writes - allowed a simple 64-bit wide memory block be used ho hold the data.

I dual ported that memory block to the avalon bus and used it to hold the addresses, length, sttaus (etc).

Gave me a multi-channel dma controller (round robin, doing one burst per channel) for not much resource use.