Need ideas on solving a weird LAN91C111 problem

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originally posted by jesse@Jun 19 2006, 03:32 PM

i can't explain the alternating behavior you are seeing; however, the clock-cycle count being proportionally higher is to be expected. that is to say, increasing the clock-speed should help you with software/packet construction tasks, but the interface to the ethernet chip will not improve.

why? the 91c111 is a pretty slow chip; a while ago we had to dial-down the performance to it using avalon wait-states (can be seen in the components/altera_avalon_lan91c111/class.ptf file) to ensure that proper timing to the chip was met in all circumstances, including dma transfers. since this time-delay is fixed, the generated sopc builder logic will insert additional delay cycles to ensure that timing to the chip is met regardless of input clock-frequency.

i'd suggest some profiling - gprof to start - between 50/100 systems to see where the discrepency is with these occasional long-latency packet transfers.

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I&#39;ve only used the performance counter so far, I&#39;ll look into gprof to see what I can figure out with that.

This is what my LAN91C111 class.ptf file says:

Read_Wait_States = "20ns";

Write_Wait_States = "20ns";

Setup_Time = "20ns";

Hold_Time = "20ns";

Is that what it should be? 20ns doesn&#39;t seem that extreme.