Honored Contributor
Honored ContributorI add some extra information to the above post.
I use Quartus Prime 17.1 and DS-5 Intel SoC FPGA Edition V5.27.1 The following is the output log I get when I try to connect the debugger to the hps. Note 1: As I said before, from the jtag uart port I get no output. Note 2: I added the grayed set var lines to the automatically generated script, in the hope they could avoid the hps hang, according to the advices I found in the fourm, but they have no effect. Connected to running target Altera - Cyclone V SoC (Dual Core) on TCP:localhost cd "C:\DS-5 Workspace" Working directory "C:\DS-5 Workspace" source /v "C:\intelFPGA\17.1\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check.py" No SYSID registers could be found. Has a peripheral description file been supplied? source /v "C:\FPGA_Q17\cv_soc_devkit_ghrd\software\spl_bsp\preloader_cr.ds" +reset system +stop Target has been reset Execution stopped in SVC mode due to a breakpoint or watchpoint: S:0x00000000 S:0x00000000 LDR pc,[pc,#24] ; [0x20] = 0xA8 WARNING(CMD315): Target is not running +wait 5s +set semihosting enabled 0 +loadfile "$sdir/uboot-socfpga/spl/u-boot-spl" 0x0 Loaded section .text: S:0xFFFF0000 ~ S:0xFFFF7093 (size 0x7094) Loaded section .rodata: S:0xFFFF7094 ~ S:0xFFFF8C21 (size 0x1B8E) Loaded section .data: S:0xFFFF8C28 ~ S:0xFFFF9AFB (size 0xED4) Entry point S:0xFFFF0000 +set debug-from *$entrypoint # Set start-at setting to address of $entrypoint +start Starting target with image C:\FPGA_Q17\cv_soc_devkit_ghrd\software\spl_bsp\uboot-socfpga\spl\u-boot-spl Running from entry point Execution stopped in SVC mode at S:0xFFFF0000 In start.S S:0xFFFF0000 39,0 _start: b reset +wait 5 +delete All user breakpoints deleted +tbreak spl_boot_device Breakpoint 2 at S:0xFFFF1498 +set var $Peripherals::$rstmgr::$rstmgr_permodrst = 0 +set var $Peripherals::$rstmgr::$rstmgr_per2modrst = 0 +set var $Peripherals::$rstmgr::$rstmgr_mpumodrst = 0 +set var $Peripherals::$rstmgr::$rstmgr_brgmodrst = 0 +set var $Peripherals::$rstmgr::$rstmgr_miscmodrst = 0 +wait 2 +set var $Peripherals::$sdr::$sdr_ctrlgrp_fpgaportrst = 0x00003fff +set var $Peripherals::$sdr::$sdr_ctrlgrp_protportdefault = 0 +cont +wait 2 ERROR(CMD360): # in C:\FPGA_Q17\cv_soc_devkit_ghrd\software\spl_bsp\preloader_cr.ds:71 while executing: wait 2 ! Wait for stopped timed out ERROR(CMD656): The script C:\FPGA_Q17\cv_soc_devkit_ghrd\software\spl_bsp\preloader_cr.ds failed to complete due to an error during execution of the script wait
