Honored Contributor
Honored Contributor--- quote start ---
my god, 14 layers is way too much... you can get a 256bga on a 6-layer, 4-layer if you don't hav etoo much high speed stuff.[/b]
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no jdhar. it is definitly not from a point of view of emc purpose.
for a 484 bga you will need up to 5 layers for fanout purposes.
you will need 1 powerplane for vio 3v3 and 1 for vcore 1v2.
both powerplanes need to be seperated by one gnd plane
each routing layer needs a gnd plane where the e and h field go to.
so if you draw such a layerstack :
1 top
2 gnd
3 vcore-plane
4 gnd
5 vio-plane
6 gnd
7 routinglayer 1
8 routinglayer 2
9 gnd
10 routinglayer 3
11 routinglayer 4
12 gnd
13 bot
this 13 layers so 1 layer left for other purposes.
be aware of that the distance between the core and gnd is 50um and between routinglayer as far away as possible.
<!--quotebegin-jdhar@Jul 31 2006, 06:33 PM 484 can get on a 6-layer very easily. i have put a 672 on an 8-layer, but it could have been dropped to 6 possibly.
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--- Quote End --- i do not see a solution of a 484 with 6 layers. 3 layers are needed at least for a power supply that is wide decoupled for signals of several hunderd MHz. to reach the inner balls of the 484 of a cyclone 2 you need 5 layers even with 4/4mil. so 8 layers would be the minimum. the question is if the pcb has to be an industrial design that can stand all approval test like burst surge TEM ..... and furthermore pass the etsi requirements if the design needs to pass. a propper powerplane design is needed if you have a clock speed of 50MHz (sinus!!) you will end up with the 5th that ist 5x50MHz meaning at least 250MHz to get a proper recangle. so your design must handle 250MHz wide low impedance powerplane. this can only be archieved with a full copper plane for gnd and for each supply with a distance of 50um. 100um woulod work but you lose the profits of the field effects that occur between the planes! to have a propper signal on you pcb (again 50MHz clock leadts to at least 250MHz) you need to have an eye on impedance and crosstalk between layers and traces. with a layerstack as mentioned above the board has a optimum signal, nearly no emission, reaches class A of emc tests and does not "recognise" any burst or surge pulse. even the TEM does not have any effect. with less layers it is possible to disturb the same design and a couple of peaks will rise during the tests between 30 and 1000 MHz. i have seen the emc tests of "eval kits" with as less as possible layers and these pcb will never pass the emc requirements !! not only the peaks are far above the limit line. again the question is for what purpose the design should be. if the design is pure digital then it could work, but if there are analog parts within the complete design where you want to find signals within the noise a bad power supply will destroy everything. we had a barcode reader design where just modifying the powersupply lead to 18% more readings leading to a better product. an rfid reader got 30% more reading distance by just modifiying the layout without changing any component or the placement (to use the paste masks again after the design change. Michael Schmitt
