My PCB design for Cyclone II ep2c20F484;ep2c35F484

I see the point of reducing the cost for each additional layer pair.

but filling the gaps with gnd polygons is not a power plane.

you will lose the profits you get from a real powerplane design such like low impedance over a wide frequency range. Image a clock of 50Mhz. 50MHz is the first frequency and just a pure sine wave. to reach a rectangle clock shape you need the upper higher frequencies like 150 250 ... so the 5th will give you 250MHz and that means your design must handle at least 250MHz bandwidth.

of course you can get design working with as less a possible layers, but i have seen a couple of pcb's that still work but have no chance to pass emc tests without shielding, ferrit beats and all these expensive stuff. we did the calculation too and we ended up that the 14layers is the cheapest solution over all to get a design that is industrial bullet proof and passes all tests with no metal housing or any shielding. and the peaks are far away from the emc or etsi limits.

filling gaps with gnd can make things more worse as you need to contact them with low impedance to each other, if not you layout some antennas and believe me they will do their job very good and radiate around :-) imagine even a via is a kind of an inductor between your gnd fills with a few pH and a few pF and a bit R so you have R L C what leeds to resonance ...

keeping an eye on the layer stack has on one side the costs for the additional layers but on the other hand you save a lot of caps you do not need to spread around the board. i have a dozend of mlc (each 100uF 6V3 1210size) around the whole pcb and 8 caps 0402 size as a calculated capacitor bank to control the power supply impedance. the copper is there just use it :-) the distance between the layers is also very important. having a distance of 100um between the layers gives you a good power plane but moving to 50um a much better as you gain the goals of field effects between them. but that goes to far here to explain, this is a fpga forum and not an emc.

if i would layout a pcb for my own purpose and will never go to any aproval test i would also try to get rid of any layer pair i can.

take care about the power supply, you will go nut if you try to find out why your design does funny things due to over and undershots. but the fpga's give you the possability to control the current of each pin.

for your layer stack ...

try to have the two power supply layers vcc vio between gnd

signal (gnd)

vcore

signal (gnd)

vcc

signal (gnd)

in this case each power layer has two gnd's one above and the other underneath so you double the cap, halve the impedance .... if your signal does not brake your gnd fills too much

also try to have vcore next to the fpga top layer.

place additional vias to connect the gnds vcc vore tracks fills ... as much as you can to lower the impedance. each signal (track) has a current that travels along this track, but always has a current that goes back ...

Michael Schmitt