Honored Contributor
Honored Contributori did a migration board with ep2c20f484 and ep2c50f848 both i8n types.
what i miss in your pcb is a proper powersupply layout. those traces conneting vio and vcore are inductance with pure impedance controled traces. imagine what will happen if several hundred or more dff inside your fpga switch from 0 to 1 or vice versa each of them with serveral mA up to hundert mA currents for a few nsec that will lead to a current peak of serveal A/nsec and if you take into account that your voltage ripple has to stay within a few mV you will need caps with low esr. C(F)=I(A) x t(nsec) / U (V) where U is the max allowed voltage ripple for a time t with a current I. F is As/V if you now look at these smal traces for the vcore and vio pins and even the gnd pins .... i doubt that you will run a stable design without taking care about gnd bounce over and undershots .... they can lead to uncontrolled switching of your logic as they move the voltage levels for a short time. My pcb for these FPGAs has 14 Layer and does not need any emc screening to pass emc and etsi approval when running under full load @ 64MHz clock. all signals are impedance controlled. the layout is the key factor for this stable design. If you have a look at the pcb design guides from altera and xilinx and other you will see that they do not take into account what is realy needed for a stable AND emc bullet proof design. Some of the hints and tips are realy false. Regards Michael Schmitt
