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Altera_Forum
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9 years ago

My AXI4 Lite slave hangs CPU after read. Write transactions work correctly

Hi, I have ported my AXI4-Lite to IPbus bridge from Zynq to Altera Cyclone V. Unfortunately, it behaves in a strange way in Cyclone V. Tests have been done with "devmem" tool in Buildroot comp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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I guess the question is whether or not removing that works better? What would be interesting is taking a look at the optimization section of the fitter to see if it is optimizing out part of the logic.

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The question is not about resources consumption but about the speed of the interface. I've speed up transactions by combinational control of ARREADY, AWREADY and some other signals. However it contradicts the statement, that "On master and slave interfaces there must be no combinatorial paths between input and output signals."

So it works, it is fast, but it does not comply to the AXI4 specification :cry:.

By the way, the whole design is available at http://opencores.org/project,ax4lbr